A research team has developed an integrated process combining pure ruthenium-based nano through-silicon via fabrication and extreme all-dry thinning of silicon-on-insulator wafers to support backside power-delivery networks for advanced three-dimensional integrated circuits, according to a new study published in Engineering.

Backside power-delivery networks have been studied to address routing congestion at technology nodes beyond 3 nm, where conventional copper-based nano through-silicon vias face issues including barrier layer constraints and diffusion risks. The researchers focused on ruthenium as a barrier-free interconnect material with strong oxidation resistance, suitable for nanoscale high-aspect-ratio structures.

Using a multi-step etching approach based on fluorine radicals and oxygen, the team created scallop-free tapered nano through-silicon via arrays with an aspect ratio up to 10.4:1.0 and critical dimension down to 39 nm. Atomic layer deposition was used to achieve void-free pure ruthenium metallization without traditional barrier stacks, yielding a resistivity of 19.9 μΩ·cm. A dry recess etching process using chlorine and oxygen plasma was established for ruthenium in these high-aspect-ratio structures, showing a selectivity ratio of ruthenium to liner oxide greater than 50:1 and effectively removing metallic sidewall residues.

For wafer processing, the team employed a sequential all-dry thinning scheme on 200-mm silicon-on-insulator wafers using the 2-μm buried oxide layer as an etch stop layer. The process included precision grinding, inductively coupled plasma deep silicon etching, and vapor-phase hydrofluoric acid removal of the buried oxide, resulting in a final top silicon thickness of 500 nm with total thickness variation below 15 nm. A plasma-assisted all-dry backside reveal technique exposed the nano through-silicon vias while maintaining sidewall dielectric liner integrity with loss below 1 nm.

Electrical characterization showed the average line resistance of ruthenium-filled nano through-silicon vias reached 29 Ω/μm. Reliability assessments included 100 thermal cycles from −40 °C to 125 °C, with relative resistance change remaining below 1%. Leakage currents stayed below 80 pA under a 6 V bias for dense arrays, and breakdown performance remained stable with leakage below 0.2 nA at 9 V. Electromigration testing under accelerated conditions showed consistent time-to-failure values, supporting stable long‑term operation.

The combined process provides a manufacturable pathway for backside power-delivery network integration, supporting the development of energy-efficient three-dimensional integrated circuit architectures through improved material and process engineering at the nanoscale.

The paper “Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network,” is authored by Biao Wang, Feifeng Huang, Qiancheng Wang, Zhao Chen, Hongbin Chen, Quan Wang, Qiu Shao, Yiqin Chen, Zhengyuan Wu, Bo Feng, Ming Ji, Huigao Duan. Full text of the open access paper: https://doi.org/10.1016/j.eng.2025.10.026. For more information about Engineering, visit the website at https://www.sciencedirect.com/journal/engineering.