As the global semiconductor industry enters the so-called "2 nm (nanometer, one-billionth of a meter) process" era, the actual size of transistors — the core components of semiconductor chips — still remains above 10 nm. How much smaller, then, can transistors actually get? KAIST researchers have developed a technology to predict that limit through quantum mechanical atom-level calculations.
KAIST (President Kwang Hyung Lee) announced on the 14th that a research team led by Professor Yong-Hoon Kim of the School of Electrical Engineering has developed a computational design technology that utilizes computer simulations to analyze and predict the scaling limits of transistors, a key challenge in developing next-generation semiconductor devices.
Transistors are ultra-small switches that turn electrical currents on and off, serving as key components that determine the performance and power efficiency of semiconductor chips that power smartphones, artificial intelligence computers, and more. The semiconductor industry has continuously downsized transistors to achieve higher performance and lower power consumption. However, when the size becomes excessively small, quantum tunneling occurs—a quantum mechanical phenomenon where electrons pass through energy barriers they normally cannot cross—making current control difficult. For this reason, identifying how much smaller transistors can be made within the boundaries of quantum tunneling is a critical task in next-generation semiconductor development.
However, it is virtually impossible to experimentally confirm the scaling limits of transistors directly. With current technology, it is difficult to precisely control and quantitatively analyze the contact area where the metal electrode and the semiconductor channel (the pathway through which current flows inside a transistor) meet at the atomic level.
The research team resolved this issue by utilizing ab initio or first-principles calculations, a method that computes material properties based solely on fundamental physics laws without relying on experimental data. The research team had previously developed and reported a new theoretical-computational framework called multi-space constrained-search density functional theory (MS-DFT), which extends the scope of first-principles calculations from materials to devices by precisely analyzing the complex quantum phenomena occurring at the interface where metal electrodes and semiconductors meet and across which electrons flow.
In this study, the team built on this framework to perform computational transfer length method (TLM) experiments, the gold standard experimental technique for extracting contact resistance (the resistance to current flow occurring at the metal electrode-semiconductor interface). Based on the atomic-level TLM calculations results, they identified the quantum tunneling limit (the length at which electrons stop leaking and begin to allow transistor current control).
The research team applied this technology to a monolayer MoS₂ (molybdenum disulfide) device, a representative two-dimensional semiconductor material that can be made as thin as an atomic layer and is a candidate material for next-generation transistor channels. As a result, they were able to quantitatively analyze how deeply electrons penetrate into the channel and how much this hinders current flow control depending on the type of metal electrode and the contact atomic geometry. In other words, they clarified that the limit to how small a transistor can be made varies depending on which metal and contact structure are selected. This implies that the performance and limits of a device can now be predicted in advance solely through computer simulations before the actual transistor fabrication.
According to the research results, the critical tunneling length—the maximum length at which electrons penetrate into the channel and begin to affect transistor operation—was found not to be a single fixed value. This length emerged as a design variable that changes depending on the work function of the metal (the minimum energy required to remove an electron from a metal) and the contact structure of the interface where the metal and semiconductor meet. This signifies that the extent to which a transistor can be downsized depends on the combination of materials and structural design.
In particular, among the candidate metal types and contact structures considered, the research team confirmed that the length where electrons stop leaking could be reduced to less than 4 nm. This result demonstrates the possibility of making transistors even smaller than the levels achieved today.
Furthermore, the research team proposed a design strategy for next-generation semiconductor chips that reduce power consumption by combining two-dimensional semiconductors with different properties.
This study is significant because it establishes a platform for predicting scaling limits and designing optimal device configurations before actually fabricating semiconductor chips. Through this, it is expected to reduce trial and error and shorten the development period in the process of developing next-generation ultra-small AI semiconductor devices.
Professor Yong-Hoon Kim said, "This study is significant because it presents a new physical criterion for defining how small next-generation transistors can become. By computationally analyzing quantum mechanical phenomena in the sub-10 nm regime, which are difficult to probe experimentally, we have opened a path toward utilizing these findings in next-generation transistor design."
The study, in which Dr. Tae Hyung Kim participated as the first author, was published online on May 28th in the prestigious computational journal 'npj Computational Materials, a prestigious journal in the field of computational materials science ※ Title of the paper: Ab initio transfer length method simulations of tunneling limits in 2D semiconductors, DOI: https://doi.org/10.1038/s41524-026-02101-1
This research was conducted with support from programs such as the Mid-Career Researcher Program and EDISON 2.0 Program of the National Research Foundation of Korea.