Researchers from the National University of Defense Technology (NUDT) in Changsha have introduced a first-of-its-kind framework, PyABV, that seamlessly integrates assertion-based verification into the PyRTL hardware design flow. PyABV enables designers to detect and analyze errors both during simulation and after silicon fabrication, addressing the common gap in weak verification support for agile hardware description languages.
Bridging Agile Hardware Design’s Verification Gap to Prevent Costly Respins
Modern hardware development increasingly relies on agile design methodologies to accelerate the prototyping and innovation process. However, these methods often lack built-in mechanisms to catch subtle design flaws early, leading to costly respins and reliability concerns in sectors from consumer electronics to critical infrastructure. By embedding familiar, industry-standard assertion techniques into a Python workflow, PyABV makes rigorous checking accessible to a broader range of developers and researchers. This advancement can streamline verification in academia and industry, inform hardware security standards, and foster more dependable devices in everyday life.
“Our goal was to bring assertion-based verification directly into the Python workflow, empowering designers to catch subtle bugs early and reduce turnaround times,” said Prof. Tun Li.
Low-Overhead Assertion Checks: <1.5% Area Impact with Comprehensive Coverage
The researchers observed several significant outcomes from applying PyABV in real-world design scenarios:
- Online Monitoring Overhead: Assertion checks during simulation increase runtime by 30%–40%, which optimized coroutines can reduce to 20%–29%.
- Minimal Area Impact: Hardware monitor circuits add less than 1.5% extra logic area across designs ranging from 5,800 to 13,000 logic units.
- Comprehensive Coverage: PyABV supports a broad set of temporal operators, allowing designers to specify and verify complex timing properties with ease.
High-Level Python Assertions Seamlessly Translate into Efficient Hardware Monitors
PyABV represents assertions as Python objects based on standard automata semantics, letting designers write temporal checks in clear, high-level code. An assertion manager integrates with the PyRTL simulator for real-time monitoring, using multithreading and coroutine techniques for efficiency. For hardware verification, each assertion is automatically translated into a dedicated monitor circuit that preserves the original verification intent during synthesis.
End-to-End Python Verification Framework Accelerates Reliable Chip Development
PyABV delivers a first-of-its-kind, end-to-end assertion verification solution within a Python-based hardware design flow. By balancing comprehensive error detection with modest performance and area overheads, it promises to boost productivity and reliability in hardware development across both research and industry. The open-source framework is now available at
https://gitee.com/TwoBNumber1/py-abv for immediate adoption and community-driven enhancements. This work was published in
Frontiers of Computer Science in January 2025 (
https://doi.org/10.1007/s11704-024-40127-0).
DOI:
10.1007/s11704-024-40127-0