A new approach could help make future AI chips smaller and more energy-efficient. A KAIST-led research team has used a single material to address one of the major obstacles facing atomically thin semiconductors, the difficulty of efficiently injecting charge. The technology could contribute to next-generation AI and low-power semiconductor devices in which multiple ultrathin layers are vertically integrated to increase device density and performance.

KAIST (President Choongsik Bae) announced on September 16 that a research team led by Professor Joonki Suh from the Department of Chemical and Biomolecular Engineering has developed a ‘universal van der Waals tunneling injector’ based on tin diselenide (SnSe₂). The single-material injector efficiently supplies charge to two different types of atomically thin semiconductor channels.

The study was conducted in collaboration with researchers from Yonsei University, the Beijing Computational Science Research Center in China, the Korea Institute of Science and Technology (KIST), Hanyang University, the Ulsan National Institute of Science and Technology (UNIST), and Samsung Electronics.

A transistor is a microscopic switch that controls the flow of electric current. Nearly every semiconductor chip, from those used in smartphones and computers to advanced AI processors, contains vast numbers of transistors.

Transistors can be broadly classified as n-type or p-type. In n-type transistors, ‘electrons’ carry the current, while in p-type transistors, current is carried by ‘holes’, which are empty electron states that act as positive charge carriers. Modern semiconductor chips combine these two types in complementary metal-oxide-semiconductor, or CMOS, circuits, which enable fast operation while minimizing power consumption.

Two-dimensional semiconductors, which can be less than a nanometer thick, have recently emerged as promising materials for making chips smaller and more energy-efficient. Their atomically thin structure also makes it possible to stack multiple device layers vertically, potentially allowing more transistors to be integrated within the same footprint.

A persistent challenge, however, has been injecting charge efficiently into such ultrathin semiconductors. Depositing a conventional metal electrode directly onto a two-dimensional semiconductor can damage its delicate atomic structure during fabrication. The resulting interface can also create an energy barrier that obstructs the injection of electrons or holes.
In atomically thin semiconductors, the ‘entry point’ for electrical charge has been a major bottleneck limiting transistor performance. Complicating matters further, n-type and p-type channels generally require different contact conditions and have therefore relied on separately optimized electrodes.

The research team addressed this problem using a single material: tin diselenide (SnSe₂), a layered semiconductor composed of tin (Sn) and selenium (Se). Instead of forming strong chemical bonds with the semiconductor channel, SnSe₂ can be placed in contact with it through weak interatomic attractions known as van der Waals forces. This approach preserves the atomically thin channel and creates a clean, uniform interface.

Crucially, SnSe₂ provides a different but favorable charge-injection pathway depending on the semiconductor with which it is paired.

When combined with p-type tungsten diselenide (WSe₂), SnSe₂ forms a type-III, or ‘broken-gap’, band alignment that enables efficient band-to-band tunneling. In this process, charge carriers pass through an energy barrier quantum mechanically rather than having to acquire enough energy to travel over it. When combined with n-type molybdenum disulfide (MoS₂), the same SnSe₂ injector forms a different junction. An applied gate field reshapes and narrows the electron-injection barrier, allowing electrons to tunnel through it.

In other words, whereas n-type and p-type transistors previously required separately optimized charge-injection contacts, SnSe₂ serves as a single, shared injector that adapts to both channel polarities through different tunneling mechanisms.

The resulting performance improvements were substantial. In p-type WSe₂ transistors, the SnSe₂ injector increased the maximum drive current by more than 1,000 times compared with conventional nickel electrodes. Drive current refers to the maximum current that a transistor can deliver when switched on.

In n-type MoS₂ transistors, the SnSe₂ injector enabled steep switching and an on/off current ratio exceeding one billion (10⁹). This means that the device conducts current effectively in its on state while strongly suppressing current in its off state.

The team also fabricated a CMOS inverter, a basic building block of digital circuits that combines n-type and p-type transistors, and confirmed that it operated reliably in response to repeated input signals.

The key contribution of this research is that it demonstrated a single material can efficiently supply charge to both types of ultrathin semiconductors, moving beyond the conventional approach of using separate electrodes for n-type and p-type devices.

With further advances in direct growth, large-area fabrication, and device integration, two-dimensional semiconductors could eventually be stacked in multiple layers to form three-dimensional chips. Such architectures could accommodate more transistors within the same footprint and perform more functions while consuming less power, contributing to the development of next-generation AI processors and ultra-low-power electronic devices.

“This study demonstrates that efficient charge injection, one of the most challenging bottlenecks in monolayer two-dimensional semiconductors, can be addressed using a single material platform,” said Professor Joonki Suh. “With further advances in direct growth and large-area processing technologies, this approach could accelerate the practical implementation of low-power two-dimensional CMOS integrated circuits.”

The study was led by KAIST PhD candidate Hanbin Cho as first author, with Professor Kyungmin Ko from Yonsei University and Professor Joonki Suh from KAIST serving as co-corresponding authors. The paper was published online on August 12 in the international journal Advanced Materials.

※ Paper title: “A Universal van der Waals Tunneling Injector for Monolayer CMOS”
※ DOI: 10.1002/adma.74597
※ Authors: Hanbin Cho of KAIST, first author; Professor Kyungmin Ko of Yonsei University and Professor Joonki Suh of KAIST, co-corresponding authors
This work was primarily supported by Samsung Electronics Co., Ltd. It also received support from Korean funding agencies, including the National Research Foundation of Korea (NRF), funded by the Ministry of Science and ICT and the Ministry of Education.