- Research background:
The advent of big data era raising significant challenges in information processing, especially in the aspect of capacity and power consumption. Situations become even worse when we consider the fact that over 90% of data information is transmitted over light wave while most of the information processing is carried out in the electrical domain. Two different strategies may be adopted to solve this problem. One strategy is to perform the optical-electrical-optical (O-E-O) conversion, while the other one is to process optical information directly in the optical domain, termed all-optical information processing (AOSP). O-E-O conversion faces optoelectronic parallelism challenges and transparency constraints. In contrast, AOSP may allow much more favorable scaling with the system complexity, cost as well as power consumption when proper nonlinear process is chosen. As early as the 1980s, AOSP had been widely explored in bulk nonlinear devices, but recent advances in its integration have driven rapid development of the technology. Among various integration platform, silicon-based photonic integration turns out to be a promising platform for the development of advanced AOSP devices and functionalities. The functionalities of AOSP are rather diverse, which strongly related to the structure of optical networks. Future optical networks require performance of 3T (format transparency, wavelength transparency, bandwidth transparency), 3M (multi-function, multi-channel, multi-network), and 3S (self-perceiving, self-learning, self-adopting). Consequently, reconfigurability and flexibility are critical to future optical networks as well as AOSP on top of ultra-large capacity.
Recently, the research team led by Prof. Xinliang Zhang from Huazhong University of Science and Technology, Prof. Yikai Su from Shanghai Jiao Tong University, Prof. Kun Qiu from the University of Electronic Science and Technology of China, and Academician Ninghua Zhu from Nankai University jointly demonstrated a monolinthically integrated programmable all-optical signal processing (AOSP) chip with filtering, regeneration, and logic operation functions. This achievement originates from a national project granted to develop silicon-based reconfigurable AOSP chips, harnessing the inherent advantages of silicon photonics—CMOS compatibility, low loss, compact size, and large optical nonlinearity—to deliver the high-speed performance, advanced modulation formats, and wavelength transparency essential for optical networks. All-optical processing functions such as reconfigurable filtering, logic, and regeneration are experimentally verified on this programmable all-optical processing chip, paving the way for transformative applications in the fields of optical communication, high-performance computing, imaging, and sensing.
- Research highlights:
There are several challenges in developing programmable AOSP SOI platform. First, silicon material suffers from carrier effects, including two-photon absorption (TPA) and free carrier absorption (FCA), which limit the maximum power available for nonlinear processes and thus reduce nonlinear effects. In addition, the strong light field confinement caused by high refractive index may lead to severe scattering losses, hindering the development of low loss integrated optical waveguides, increasing the complexity to fine manipulate light fields, as well as introducing severe optical and thermal crosstalk. These challenges are addressed by developing new fabrication processes, structures and incorporating new materials. Firstly, by promoting key manufacturing technologies and device structures, ultra-low loss silicon-based waveguides and microresonators with ultra-high-quality factor have been developed. Integrated photonic filter with ultra-wide range of reconfigurable bandwidth and free spectral range, enabling precise manipulation and selection of input light fields with high degrees of freedom, is developed. Secondly, several mechanisms and new designs aimed at enhancing nonlinearity have been proposed, including ridge waveguides with reverse biased PIN junctions, slot waveguides, multimode waveguides, and parity-time symmetry coupled microresonators. These novel designs enable several advanced AOSP operations. That is, we demonstrated 100 Gbit/s logic computing using a self-developed single-chip integrated programmable optical logic array. High-dimensional multi-value logic operations based on the four-wave mixing effect is also demonstrated. With ultra-efficient Si PIN waveguides, multi-channel all-optical amplitude and phase regeneration are successfully realized, enabling multi-channel, multi-format, and reconfigurable all-optical regeneration function on chip. The ability to expand regeneration capacity through spatial dimensions is also verified. Thirdly, the crosstalk from optical as well as thermal coupling due to high-density integration are mitigated by developing novel optical designs and advanced packaging technologies, enabling high-density, small size, multi-channel and multi-functional operation with low power consumption. Finally, four programmable AOSP chips are developed, i.e., programmable photonic filter chip, programmable photonic logic operation chip, multi-dimensional all-optical regeneration chip, and multi-channel and multi-functional AOSP chip with packaging.
3）Summary and Outlook
This study highlights the key progress in the development of programmable AOSP chips. Through structural and material innovation, key challenges in building large-scale integrated AOSP photonic chips have been addressed, such as high transmission loss, weak nonlinear effects, limited optical field control, and severe optical, electrical, and thermal crosstalk. The loss of ultra-low loss silicon waveguide is as low as 0.17dB/cm, and the Q factor is as high as 2.1106. We have achieved advanced integrated filters with a bandwidth that can be tuned from 0.55 pm to 648.72 pm (i.e. tuned by more than three orders of magnitude), as well as FSR that can be tuned from 0.06 nm to 1.86 nm (30 times). The absolute FWM conversion efficiency has been proven to be as high as 12 dB, and such high efficiency is crucial for ensuring the success of high-performance logic and regeneration operations. Eight channel multifunctional single-chip integration of filtering, logic, and regeneration has been achieved, integrating 136 devices (including filters, logic gates, regenerators, gratings, MMIs, electrodes, etc.) on a single chip. It has been proven that the total signal processing capability is up to 800 Gb/s (running at 100 Gb/s per channel), and can accommodate multiple modulation formats, including DPSK and OOK. A complete set of CLU has been generated for logical operations, and QPSK regeneration has been proven to increase receiver sensitivity by more than 6dB. By utilizing advanced optoelectronic packaging technology, the chip level routing and processing of multi-channel signals have been validated. Due to the inherent ultrafast nature of optical Kerr nonlinearity (on femtosecond timescales), these efforts have laid the foundation for designing and manufacturing larger scale silicon-based AOSP chips at higher speeds. Looking ahead, improvements in nanomanufacturing technology, new materials, and packaging processes are expected to further enhance the performance and flexibility of AOSP chips, highlighting high-efficient and high-density information processing in future classical and non-classical communication and computing applications.
DOI:
10.1007/s12200-025-00154-6