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UPC researchers have discovered a technique to produce cheaper and more flexible multiple thin crystalline silicon wafers
12 June 2013
Universitat Politècnica de Catalunya (UPC)
A team of researchers from the Nanoengineering Research Centre (CRNE) and the Department of Electronic Engineering at the Universitat Politècnica de Catalunya · BarcelonaTech (UPCn has found a way to make the manufacture of crystalline silicon materials faster and more affordable. The results of their research have recently been published in the online version of the landmark journal Applied Physics Letters.
Thin crystalline silicon wafers measuring around 10 µm (micres) are costly but also very sought after in the field of microelectronics, especially in view of the growing demand for 3D circuit integration with microchips. Silicon wafers also have potential photovoltaic applications in the medium term in the conversion of sunlight to electricity and the production of more affordable, more flexible and lighter solar cells.
In recent years, techniques have been developed to obtain increasingly thinner crystalline silicon wafers from monocrystalline cylindrical ingots. Layers cut from the ingots using a multithreaded saw impregnated with abrasive material have a minimum thickness of around 150 µm. Obtaining wafers that are any thinner is more complicated, as existing methods only allow such wafers to be obtained one at a time. Furthermore, 50% of the silicon is lost in the process.
The technology developed by the research team – David Hernández, Trifon Trifonov and Moisés Garín, led by Professor Ramon Alcubilla – enables a large number of crystalline layers, controlled for thickness, to be produced from a single crystalline silicon wafer in just a single step. The outcome is a kind of crystalline silicon “millefeuille” produced more efficiently, more rapidly and more affordably than by existing methods.
The methodology developed by the scientists is based on making small pores in the material and applying a high temperature during the manufacturing process. Multiple separate crystalline silicon wafers are obtained by carefully controlling the pore profiles. Precise control over diameter controls both the number of layers and their thickness. The millefeuille silicon layers are then separated by exfoliation. The resulting number of silicon layers is determined by the thickness of the layers themselves and the initial thickness of the wafer. The CRnE researchers have succeeded in creating up to 10 thin wafers (5-7mm thick) from a single 300 mm thick wafer.
Reduced costs for industry
The demand for thin and ultra-thin crystalline silicon wafers responds to the application possibilities offered by 3D circuit integration of micro-electromechanical systems (MEMS) with conventional microchips and also to the latest generation of photovoltaic technology. Wafer cutting for solar cell production, for example, has been steadily improving. Thickness has been reduced (350 mm in the 1990s to 180 mm currently) while efficiency has been enhanced, resulting in reduced manufacturing costs; nonetheless, greater reductions are likely to be difficult to achieve. It has been shown that, despite lesser thickness, the wafers retain a high capacity to absorb solar energy and convert it into electricity.
Researcher Moisés Garín in the clean room, treating a wafer before putting it in the oven.
Researcher Moisés Garín in the clean room, putting the wafer in the oxidation oven at 1,100 degrees Celsius.
Exposure of the wafer during the lithographic process.
A high-temperature oven in the clean room.
A silicon sample after being removed from the cylinder.